View AK4626AVQ_2610181.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [ak4626a] ms0397-e-00 2005/06 - 1 - general description the ak4626a is a single chip codec that includes two channels of adc and six channels of dac. the adc outputs 24bit data and the dac accepts up to 24bit input data. the adc has the enhanced dual bit architecture with wide dynamic range. the dac introduces the newly developed advanced multi-bit architecture, and achieves wider dynamic range and lower outband noise. an auxiliary digital audio input interface maybe used instead of the adc for passing audio data to the primary audio output port. control may be set directly by pins or programmed through a separate serial interface. the ak4626a has a dynamic range of 102db for adc, 106db for dac and is well suited for digital surround for home theater and car audio. an ac-3 system can be built with a iec60958(spdif) receiver such as the ak4112b. the ak4626a is available in a small 44pin lqfp package which will reduce system space. *ac-3 is a trademark of dolby laboratories. features ? 2ch 24bit adc - 64x oversampling - sampling rate up to 96khz - linear phase digital anti-alias filter - single-ended input - s/(n+d): 92db - dynamic range, s/n: 102db - digital hpf for offset cancellation - i/f format: msb justified, i 2 s or tdm - overflow flag ? 6ch 24bit dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - single-ended outputs - on-chip switched-capacitor filter - s/(n+d): 90db - dynamic range, s/n: 106db - i/f format: msb justified, lsb justified(20bit,24bit), i 2 s or tdm - individual channel digital volume with 128 levels and 0.5db step - soft mute - de-emphasis for 32khz, 44.1khz and 48khz - zero detect function ? high jitter tolerance ? ttl level digital i/f ? 3-wire serial and i 2 c bus p i/f for mode setting ? master clock:256fs, 384fs or 512fs for fs=32khz to 48khz 128fs, 192fs or 256fs for fs=64khz to 96khz 128fs for fs=120khz to 192khz ? power supply: 4.5 to 5.5v ? power supply for output buffer: 2.7 to 5.5v ? small 44pin lqfp ? ak4626 pin compatible high performance multi- channel audio codec ak4626 a
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 2 - ? block diagram audio i/f lpf lpf dac datt lpf dac datt lpf dac datt lpf dac datt lpf dac datt lout1 rout1 lout2 rout2 lout3 rout3 dac datt ak4626a adc hpf adc hpf rin lin lrck bick sdout1 sdout2 sdout3 ac3 sdin mcko lrck bick xti xto dir sdto ak4112b rx4 rx3 rx2 rx1 lrck bick sdti1 sdti2 sdti3 daux sdos mclk lrck bick sdout sdin1 sdin2 sdin3 mclk sdto format converter block diagram (dir and ac-3 dsp are external parts)
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 3 - ? ordering guide AK4626AVQ -40 +85 c 44pin lqfp(0.8mm pitch) akd4626 evaluation board for ak4626a ? pin layout s dos tdm0 1 i2c 44 2 s mute 3 b ick 4 l rck 5 s dti1 6 s dti2 7 s dti3 8 s dto 9 daux 10 dfs0 11 loop0/sda/cdti 43 dif1/scl/cclk 42 41 40 mclk 39 dzf1 38 a vss 37 avdd 36 vrefh 35 vcom 34 tst1 12 dzfe 13 tvdd 14 dvdd 15 dvss 16 17 tst2 18 cad1 19 cad0 20 tst3 21 tst4 22 33 32 31 30 29 28 27 26 25 24 23 dzf2/ovf rin lin nc tst5 rout1 lout1 rout2 lout2 rout3 lout3 AK4626AVQ top vi ew pdn dif0/csn p/s
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 4 - ? compatibility with ak4527b 1. functions functions ak4527b ak4626a dac sampling frequency up to 96khz up to 192khz tdm128 (96khz) not available available digital attenuator 256 levels 128 levels soft mute soft mute function is independent of digital attenuator. soft mute function is not independent of digital attenuator. analog input (adc) differential input single-ended input 2. pin configuration pin# ak4527b ak4626a 11 dfs dfs0 12 nc tst1 18 test tst2 19 nc cad1 20 adif cad0 21 cad1 tst3 22 cad0 tst4 29 lin- tst5 30 lin+ nc 31 rin- lin 32 rin+ rin 44 loop1 tdm0 3. register addr ak4527b ak4626a 00h not available tdm0 00h not available tdm1 01h dfs dfs0 01h not available dfs1 09h not available ats1, ats0 0ah not available dzfm3
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 5 - pin/function no. pin name i/o function 1 sdos i sdto source select pin (note 1) ?l?: internal adc output, ?h?: daux input sdos pin should be set to ?l? when tdm= ?1?. 2 i2c i control mode select pin ?l?: 3-wire serial, ?h?: i 2 c bus 3 smute i soft mute pin (note 1) when this pin goes to ?h?, soft mute cycle is initialized. when returning to ?l?, the output mute releases. 4 bick i audio serial data clock pin 5 lrck i input channel clock pin 6 sdti1 i dac1 audio serial data input pin 7 sdti2 i dac2 audio serial data input pin 8 sdti3 i dac3 audio serial data input pin 9 sdto o audio serial data output pin 10 daux i aux audio serial data input pin 11 dfs0 i double speed sampling mode pin (note 1) ?l?: normal speed, ?h?: double speed 12 tst1 i test pin this pin should be connected to dvss. 13 dzfe i zero input detect enable pin ?l?: mode 7 (disable) at parallel mode, zero detect mode is selectable by dzfm3-0 bits at serial mode ?h?: mode 0 (dzf1 is and of all six channels) 14 tvdd - output buffer power supply pin, 2.7v 5.5v 15 dvdd - digital power supply pin, 4.5v 5.5v 16 dvss - digital ground pin, 0v 17 pdn i power-down & reset pin when ?l?, the ak4626a is powered-down and the control registers are reset to default state. if the state of p/s or cad1-0 changes, then the ak4626a must be reset by pdn. 18 tst2 i test pin this pin should be connected to dvss. 19 cad1 i chip address 1 pin 20 cad0 i chip address 0 pin 21 tst3 o test pin this pin should be left floating. 22 tst4 o test pin this pin should be left floating.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 6 - no. pin name i/o function 23 lout3 o dac3 lch analog output pin 24 rout3 o dac3 rch analog output pin 25 lout2 o dac2 lch analog output pin 26 rout2 o dac2 rch analog output pin 27 lout1 o dac1 lch analog output pin 28 rout1 o dac1 rch analog output pin 29 tst5 i test pin (internal pull-down pin) this pin should be left floating or connected to avss. 30 nc - no connect no internal bonding. 31 lin i lch analog input pin 32 rin i rch analog input pin dzf2 o zero input detect 2 pin (note 2) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan pin is ?0?, this pin goes to ?h?. it always is in ?l? when p/s is ?h?. 33 ovf o analog input overflow detect pin (note 3) this pin goes to ?h? if the analog input of lch or rch overflows. 34 vcom o common voltage output pin, avdd/2 large external capacitor around 2.2f is used to reduce power-supply noise. 35 vrefh i positive voltage reference input pin, avdd 36 avdd - analog power supply pin, 4.5v 5.5v 37 avss - analog ground pin, 0v 38 dzf1 o zero input detect 1 pin (note 2) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan pin is ?0?, this pin goes to ?h?. output is selected by setting dzfe pin when p/s is ?h?. 39 mclk i master clock input pin 40 p/s i parallel/serial select pin ?l?: serial control mode, ?h?: parallel control mode dif0 i audio data interface format 0 pin in parallel control mode 41 csn i chip select pin in 3-wire serial control mode this pin should be connected to dvdd at i 2 c bus control mode dif1 i audio data interface format 1 pin in parallel control mode 42 scl/cclk i control data clock pin in serial control mode i2c = ?l?: cclk (3-wire serial), i2c = ?h?: scl (i 2 c bus) loop0 i loopback mode 0 pin in parallel control mode enables digital loop-back from adc to 3 dacs. 43 sda/cdti i/o control data input pin in serial control mode i2c = ?l?: cdti (3-wire serial), i2c = ?h?: sda (i 2 c bus) 44 tdm0 i tdm i/f format mode pin (note 1) ?l?: normal mode, ?h?: tdm mode notes: 1. sdos, smute, dfs0, and tdm0 pins are ored with register data if p/s = ?l?. 2. the group 1 and 2 can be selected by dzfm3-0 bits if p/s = ?l? and dzfe = ?l?. 3. this pin becomes ovf pin if ovfe bit is set to ?1? at serial control mode. 4. all digital input pins except for pull-down should not be left floating.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 7 - absolute maximum ratings (avss, dvss=0v; note 5) parameter symbol min max units power supplies analog digital output buffer |avss-dvss| (note 6) avdd dvdd tvdd ? gnd -0.3 -0.3 -0.3 - 6.0 6.0 6.0 0.3 v v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage (expect lrck, bick pins) (lrck, bick pins) vind1 vind2 -0.3 -0.3 dvdd+0.3 tvdd+0.3 v v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c notes: 5. all voltages with respect to ground. 6. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 5) parameter symbol min typ max units power supplies (note 7) analog digital output buffer avdd dvdd tvdd 4.5 4.5 2.7 5.0 5.0 5.0 5.5 5.5 5.5 v v v notes: 5. all voltages with respect to ground. 7. the power up sequence between avdd, dvdd and tvdd is not critical. do not turn off only the ak4626a under the condition that a surrounding device is powered on and the i2c bus is in use. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 8 - analog characteristics (ta=25 c; avdd, dvdd, tvdd=5v; avss, dvss=0v; vrefh=avdd; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at 48khz, 20hz~40khz at fs=96khz, 20hz~40khz at fs=192khz; unless otherwise specified) parameter min typ max units adc analog input characteristics resolution 24 bits s/(n+d) (-0.5dbfs) fs=48khz fs=96khz 84 - 92 86 db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db s/n (note 8) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.3 db gain drift 20 - ppm/ c input voltage ain=0.62xvrefh 2.90 3.10 3.30 vpp input resistance (note 9) 15 25 k ? power supply rejection (note 10) 50 db dac analog output characteristics resolution 24 bits s/(n+d) fs=48khz fs=96khz fs=192khz 80 78 - 90 88 88 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 88 94 - - 106 100 106 100 106 db db db db db s/n (note 11) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 88 94 - - 106 100 106 100 106 db db db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6xvrefh 2.75 3.0 3.25 vpp load resistance 5 k ? power supply rejection (note 10) 50 db notes: 8. s/n measured by ccir-arm is 98db(@fs=48khz). 9. input resistance is 16k ? typically at fs=96khz. 10. psr is applied to avdd, dvdd and tvdd with 1khz, 50mvpp. vrefh pin is held a constant voltage. 11. s/n measured by ccir-arm is 102db(@fs=48khz).
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 9 - parameter min typ max units power supplies power supply current (avdd+dvdd+tvdd) normal operation (pdn = ?h?) avdd fs=48khz,96khz fs=192khz dvdd+tvdd fs=48khz (note 12) fs=96khz fs=192khz power-down mode (pdn = ?l?) tst=?l? (note 13) 45 34 18 24 27 80 67 51 27 36 40 200 ma ma ma ma ma a notes: 12. tvdd=0.1ma(typ). 13. in the power-down mode. all digital input pins including clock pins (mclk, bick, lrck) are held dvss.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 10 - filter characteristics (ta=25 c; avdd, dvdd=4.5 5.5v; tvdd=2.7 5.5v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 14) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay (note 15) gd 16 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 14) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband (note 14) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 15) gd 19.2 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz (note 16) 80.0khz (note 16) fr fr fr 0.2 0.3 1.0 db db db notes: 14. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs. 15. the calculating delay time which occurred by digital filtering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. 40.0khz; fs=96khz , 80.0khz; fs=192khz. dc characteristics (ta=25 c; avdd, dvdd=4.5 5.5v; tvdd=2.7 5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (sdto, lrck, bick pin: iout=-100a) (dzf1, dzf2/ovf pins: iout=-100a) low-level output voltage (sdto, dzf1, dzf2/ovf pins: iout= 100a) (sda, lrck, bick pin: iout= 3ma) voh voh vol vol tvdd-0.5 avdd-0.5 - - - - - - - - 0.5 0.4 v v v v input leakage current (note 17) iin - - 10 a note 17: tst2 pin has an internal pull-down device, nominally 100kohm.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 11 - switching characteristics (ta=-40 c 85 c; avdd, dvdd=4.5 5.5v; tvdd=2.7 5.5v; c l =20pf) parameter symbol min typ max units master clock timing 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck timing normal mode (tdm0= ?0?, tdm1= ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 45 48 96 192 55 khz khz khz % tdm256 mode (tdm0= ?1?, tdm1= ?0?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) lrck frequency ?h? time ?l? time fsd tlrh tlrl 64 1/128fs 1/128fs 96 khz ns ns audio interface timing normal mode (tdm0= ?0?, tdm1= ?0?) bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 18) bick ? ? to lrck edge (note 18) lrck to sdto(msb) bick ? ? to sdto sdti1-3,daux hold time sdti1-3,daux setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 32 32 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns ns tdm256 mode (tdm0= ?1?, tdm1= ?0?) bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 18) bick ? ? to lrck edge (note 18) bick ? ? to sdto sdti1 hold time sdti1 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 18) bick ? ? to lrck edge (note 18) bick ? ? to sdto sdti1-2 hold time sdti1-2 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns notes: 18. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 12 - parameter symbol min typ max units control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 19) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz s s s s s s s s s s ns power-down & reset timing pdn pulse width (note 20) pdn ? ? to sdto valid (note 21) tpd tpdv 150 522 ns 1/fs notes: 19. data must be held for sufficient time to bridge the 300 ns transition time of scl. 20. the ak4626a can be reset by bringing pdn ?l? to ?h? upon power-up. 21. these cycles are the number of lrck rising from pdn rising. 22. i 2 c is a registered trademark of philips semiconductors.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 13 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd lrck vih vil tbck tbckl vih tbckh bick vil clock timing (tdm= ?0?) 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil clock timing (tdm= ?1?)
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 14 - tlrb lrck vih bick vil tlrs sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm= ?0?) tlrb lrck vih bick vil sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm= ?1?)
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 15 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing (3-wire serial mode) csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing (3-wire serial mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn tpdv sdto 50%tvdd vih power-down & reset timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 16 - operation overview ? system clock the external clocks, which are required to operate the ak4626a, are mclk, lrck and bick. mclk should be synchronized with lrck but the phase is not critical. there are two methods to set mclk frequency. in manual setting mode (acks = ?0?: default), the sampling speed is set by dfs0, dfs1 (table 1). the frequency of mclk at each sampling speed is set automatically. (table 2, 3, 4). in auto setting mode (acks = ?1?), as mclk frequency is detected automatically (table 5), and the internal master clock becomes the appropriate frequency (table 6), it is not necessary to set dfs. external clocks (mclk, bick) should always be present whenever the ak4626a is in normal operation mode (pdn = ?h?). if these clocks are not provided, the ak4626a may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not pr esent, the ak4626a should be in the power-down mode (pdn = ?l?) or in the reset mode (rstn = ?0?). after exiting reset at power-up etc., the ak4626a is in the power-down mode until mclk and lrck are input. dfs1 dfs0 sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz default 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck mclk (mhz) bick (mhz) fs 256fs 384fs 512fs 64fs 32.0khz 8.1920 12.2880 16.3840 2.0480 44.1khz 11.2896 16.9344 22.5792 2.8224 48.0khz 12.2880 18.4320 24.5760 3.0720 table 2. system clock example (normal speed mode @manual setting mode) lrck mclk (mhz) bick (mhz) fs 128fs 192fs 256fs 64fs 88.2khz 11.2896 16.9344 22.5792 5.6448 96.0khz 12.2880 18.4320 24.5760 6.1440 table 3. system clock example (double speed mode @manual setting mode) (note: at double speed mode(dfs1= ?0?, dfs0 = ?1?), 128fs and 192fs are not available for adc.) lrck mclk (mhz) bick (mhz) fs 128fs 192fs 256fs 64fs 176.4khz 22.5792 - - 11.2896 192.0khz 24.5760 - - 12.2880 table 4. system clock example (quad speed mode @manual setting mode) (note: at quad speed mode(dfs1= ?1?, dfs0 = ?0?) are not available for adc.)
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 17 - mclk sampling speed 512fs normal 256fs double 128fs quad table 5. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 256fs 512fs sampling speed 32.0khz - - 16.3840 44.1khz - - 22.5792 48.0khz - - 24.5760 normal 88.2khz - 22.5792 - 96.0khz - 24.5760 - double 176.4khz 22.5792 - - 192.0khz 24.5760 - - quad table 6. system clock example (auto setting mode) ? de-emphasis filter the ak4626a includes the digital de-emphasis filter (tc=50/15s ) by iir filter. de-emphasis filter is not available in double speed mode and quad speed mode. this filter corresponds to three sampling frequencies (32khz, 44.1khz, 48khz). de-emphasis of each dac can be set individually by register data of dema1-c0 (dac1: dema1-0, dac2: demb1-0, dac3: demc1-0, see ?register definitions?). mode sampling speed dem1 dem0 dem 0 normal speed 0 0 44.1khz 1 normal speed 0 1 off 2 normal speed 1 0 48khz 3 normal speed 1 1 32khz default table 7. de-emphasis control ? digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with sampling rate (fs).
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 18 - ? audio serial interface format when tdm= ?l?, four modes can be selected by the dif1-0 as shown in table 8. in all modes the serial data is msb-first, 2?s compliment format. the sdto is clocked out on the falling edge of bick and the sdti/daux are latched on the rising edge of bick. figures 1 4 shows the timing at sdos = ?l?. in this case, the sdto outputs the adc output data. when sdos = ?h?, the data input to daux is converted to sdto?s format and output from sdto. mode 2, 3, 6, 7, 10, 11 in sdti input formats can be used for 16-20bit data by zeroing the unused lsbs. lrck bick mode tdm 1 tdm0 dif1 dif0 sdto sdti1-3, daux i/o i/o 0 0 0 0 0 24bit, left justified 20bit, right justified h/l i 48fs i 1 0 0 0 1 24bit, left justified 24bit, right justified h/l i 48fs i 2 0 0 1 0 24bit, left justified 24bit, left justified h/l i 48fs i default 3 0 0 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i table 8. audio data formats (normal mode) the audio serial interface format becomes the tdm mode if tdm0 pin is set to ?h?. in the tdm256 mode, the serial data of all dac (six channels) is input to the sdti1 pin. the inpu t data to sdti2-3 pins are ignor ed. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be 1/256fs at le ast. four modes can be selected by the dif1-0 as shown in table 9. in all modes the serial data is msb-first, 2?s compliment format. the sdto is clocked out on the falling edge of bick and the sdti1 are latched on the rising edge of bick . sdos and loop1-0 should be set to ?0? at the tdm mode. tdm128 mode can be set by tdm1 as show in table10. in double speed mode, the serial data of dac (four channels; l1, r1, l2, r2) is input to the sdti1 pin. other two data (l3, r3) are input to the sdti2. tdm0 pin and tdm0 register should be set to ?h? if tdm256 mode is selected. tdm0 pin and tdm0 register, tdm1 register should be set to ?h? if double speed mode is selected in tdm128 mode. lrck bick mode tdm 1 tdm0 di f1 dif0 sdto sdti1 i/o i/o 4 0 1 0 0 24bit, left justified 20bit, right justified i 256fs i 5 0 1 0 1 24bit, left justified 24bit, right justified i 256fs i 6 0 1 1 0 24bit, left justified 24bit, left justified i 256fs i 7 0 1 1 1 24bit, i 2 s 24bit, i 2 s i 256fs i table 9. audio data formats (tdm256 mode) lrck bick mode tdm 1 tdm0 dif1 dif0 sdto sdti1, sdti2 i/o i/o 8 1 1 0 0 24bit, left justified 20bit, right justified i 128fs i 9 1 1 0 1 24bit, left justified 24bit, right justified i 128fs i 10 1 1 1 0 24bit, left justified 24bit, left justified i 128fs i 11 1 1 1 1 24bit, i 2 s 24bit, i 2 s i 128fs i table 10. audio data formats (tdm128 mode)
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 19 - lrck bick(64fs) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 1. mode 0 timing lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 2. mode 1 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti ( i ) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 3. mode 2 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 3 22 23 24 25 0 0 1 sdti ( i ) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 4. mode 3 timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 20 - 256 bick bick(256fs) sdto(o) sdti1(i) 22 0 lch 32 bick 18 0 l1 32 bick 18 0 r1 32 bick 18 0 l2 32 bick 18 0 r2 32 bick 18 0 l3 32 bick 18 0 r3 32 bick 18 0 32 bick 18 0 32 bick 22 0 rch 32 bick 22 23 19 19 19 19 19 23 19 19 19 23 19 lrck figure 5. mode 4 timing 256 bick bick(256fs) sdto(o) sdti1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 32 bick 22 0 32 bick 22 0 rch 32 bick 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck figure 6. mode 5 timing 256 bick bick(256fs) sdto(o) sdti1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 32 bick 22 0 32 bick 22 0 rch 32 bick 22 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck figure 7. mode 6 timing 256 bick bick(256fs) sdto(o) sdti1(i) 23 0 lch 32 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 32 bick 23 0 32 bick 23 0 rch 32 bick 23 23 lrck figure 8. mode 7 timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 21 - 128 bick bick(128fs) sdto(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 sdti1(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrck sdti2(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 figure 9. mode 8 timing 128 bick bick(128fs) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrck sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 figure 10. mode 9 timing 128 bick bick(128fs) sdto(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 lrck sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 figure 11. mode 10 timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 22 - 128 bick bick(128fs) sdto(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 lrck figure 12. mode 11 timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 23 - ? overflow detection the ak4626a has overflow detect function for analog input. overflow detect function is enable if ovfe bit is set to ?1? at serial control mode. ovf pin goes to ?h? if analog input of lch or rch overflows (more than -0.3dbfs). ovf output for overflowed analog input has the same group delay as adc (gd = 16/fs = 333 s @fs=48khz). ovf is ?l? for 522/fs (=11.8ms @fs=48khz) after pdn = ? ?, and then overflow detection is enabled. ? zero detection the ak4626a has two pins for zero detect flag outputs. channel grouping can be selected by dzfm3-0 bits if p/s = ?l? and dzfe = ?l? (table 11). dzf1 pin corresponds to the group 1 channels and dzf2 pin corresponds to the group 2 channels. however dzf2 pin becomes ovf pin if ovfe bit is set to ?1?. zero detection mode is set to mode 0 if dzfe= ?h? regardless of p/s pin. dzf1 is and of all six channels and dzf2 is disabled (?l?) at mode 0. table 12 shows the relation of p/s, dzfe, ovfe and dzf. when the input data of all channels in the group 1(group 2) are continuously zeros for 8192 lrck cycles, dzf1(dzf2) pin goes to ?h?. dzf1(dzf2) pin immediately goes to ?l? if input data of any channels in the group 1(group 2) is not zero after going dzf1(dzf2) ?h?. dzfm aout mode 3 2 1 0 l1 r1 l2 r2 l3 r3 0 0 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 1 0 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 2 0 0 1 0 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 3 0 0 1 1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 4 0 1 0 0 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 5 0 1 0 1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 6 0 1 1 0 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 7 0 1 1 1 disable (dzf1=dzf2 = ?l?) 8 1 0 0 0 9 1 0 0 1 not available 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 disable (dzf1=dzf2 = ?l?) default table 11. zero detect control p/s pin dzfe pin ovfe bit dzf mode dzf1 pin dzf2/ovf pin ?l? disable mode 7 ?l? ?l? ?h? (parallel mode) ?h? disable mode 0 and of 6ch ?l? ?0? selectable selectable selectable ?l? ?1? selectable selectable ovf output ?0? mode 0 and of 6ch ?l? ?l? (serial mode) ?h? ?1? mode 0 and of 6ch ovf output table 12. dzf1-2 pins outputs
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 24 - ? digital attenuator the ak4626a has channel-independent digital attenuator (128 levels, 0.5db step). attenuation level of each channel can be set by each att7-0 bits (table 13). att7-0 attenuation level 00h 0db 01h -0.5db 02h -1.0db : : 7dh -62.5db 7eh -63db 7fh mute (- ) : feh mute (- ) ffh mute (- ) default table 13. attenuation level of digital attenuator transition time between set values of att7-0 bits can be selected by ats1-0 bits (table 14). transition between set values is the soft transition. therefore, the switching noise does not occur in the transition. mode ats1 ats0 att speed 0 0 0 1792/fs 1 0 1 896/fs 2 1 0 256/fs 3 1 1 256/fs default table 14. transition time between set values of att7-0 bits the transition between set values is soft transition of 1792 levels in mode 0. it takes 1792/fs (37.3ms@fs=48khz) from 00h(0db) to 7fh(mute) in mode 0. if pdn pin goes to ?l?, the atts are initialized to 00h. the atts are 00h when rstn = ?0?. when rstn return to ?1?, the atts fade to their current value.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 25 - ? soft mute operation soft mute operation is performed at digital domain. when the smute pin goes to ?h?, the output signal is attenuated by - during att_data att transition time (table 14) from the current att level. when the smute pin is returned to ?l?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation dzf1,2 att level - a ou t 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 14). for example, in normal speed mode, this time is 1792lrck cycles (1792/fs) at att_data=00h. att transition of the soft-mute is from 00h to 7fh (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at all the channels of the group are continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if the input data of either channel of the group are not zero after going dzf ?h?. figure 13. soft mute and zero detection ? system reset the ak4626a should be reset once by bringing pdn = ?l? upon power-up. the ak4626a is powered up and the internal timing starts clocking by lrck ? ? after exiting reset and power down state by mclk. the ak4626a is in the power-down mode until mclk and lrck are input.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 26 - ? power-down the adc and dacs of ak4626a are placed in the power-down mode by bringing pdn ?l? and both digital filters are reset at the same time. pdn ?l? also reset the control registers to their default values. in the power-down mode, the analog outputs go to vcom voltage and dzf1-2 pins go to ?l?. this reset should always be done after power-up. in case of the adc, an analog initialization cycle starts after exiting the power-down mode. therefore, the output data, sdto becomes available after 522 cycles of lrck clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are vcom voltage during the initialization. figure 14 shows the sequences of the power-down and the power-up. the adc and all dacs can be powered-down individually by pwadn and pwdan bits. in this case, the internal register values are not initialized. when pwadn = ?0?, sdto goes to ?l?. when pwdan = ?0?, the analog outputs go to vcom voltage and dzf1-2 pins go to ?h?. because some click noise occurs, the analog output should muted externally if the click noise influences system application. a dc internal state pdn 522/fs normal operation power-down init cycle normal operation (1) don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation power-down normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd external mute mute on gd (3) (3) (4) (5) (6) (6) (9) 516/fs init cycle (2) dzf1/dzf2 (7) (8) 10 11/fs (10) notes: (1) the analog part of adc is initialized after exiting the power-down state. (2) the analog part of dac is initialized after exiting the power-down state. (3) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (4) adc output is ?0? data at the power-down state. (5) click noise occurs at the end of initialization of the analog part. please mute the digital output externally if the click noise influences system application. (6) click noise occurs at the falling edge of pdn and at 512/fs after the rising edge of pdn. (7) when the external clocks (mclk, bick and lrck) are stopped, the ak4626a should be in the power down mode. (8) dzf pins are ?l? in the power-down mode (pdn = ?l?). (9) please mute the analog output externally if the click noise (6) influences system application. (10) dzf= ?l? for 10 11/fs after pdn= ? ?. figure 14. power-down/up sequence example
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 27 - ? reset function when rstn = ?0?, adc and dacs are powered-down but the internal register are not initialized. the analog outputs go to vcom voltage, dzf1-2 pins go to ?h? and sdto pin goes to ?l?. because some click noise occurs, the analog output should muted externally if the click noise influences system application. figure 15 shows the power-up sequence. a dc internal state rstn bit normal operation digital block power-down normal operation don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 (7) internal rstn bit digital block power-down 1~2/fs (9) 4~5/fs (9) 4 5/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of adc is initialized after exiting the reset state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is ?0? data at the power-down state. (4) click noise occurs when the internal rstn bit becomes ?1?. please mute the digital output externally if the click noise influences system application. (5) the analog outputs go to vcom voltage. (6) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 1 2/fs after rstn bit becomes ?1?. this noise is output even if ?0? data is input. (7) the external clocks (mclk, bick and lrck) can be stopped in the reset mode. when exiting the reset mode, ?1? should be written to rstn bit after the external clocks (mclk, bick and lrck) are fed. (8) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 6~7/fs after rstn bit becomes ?1?. (9) there is a delay, 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. figure 15. reset sequence example
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 28 - ? serial control interface the ak4626a can control its functions via registers. internal registers may be written by 2 types of control mode. the chip address is determined by the state of the cad0 and cad1 inputs. pdn = ?l? initializes the registers to their default values. writing ?0? to the rstn bit can initialize the internal timing circuit. but in this case, the register data is not be initialized. when the state of p/s pin is changed, the ak4626a should be reset by pdn pin. * writing to control register is invalid when pdn = ?l?. * ak4626a does not support the read command. (1) 3-wire serial control mode (i2c = ?l?) internal registers may be written to the 3 wire p interface pins (csn, cclk and cdti). the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 16. 3-wire serial control i/f timing
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 29 - (2) i 2 c-bus control mode (i2c= ?h?) ak4626a supports the standard-mode i 2 c-bus (max:100khz). then ak4626a does not support a fast-mode i 2 c-bus system (max:400khz). the csn pin s hould be connected to dvdd at the i 2 c-bus mode. figure 17 shows the data transfer sequence at the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 21). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) (figure 18). the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify the specific device on the bus. the hard-wired input pins (cad1 pin and cad0 pin) set them. if the slave address match that of the ak4626a and r/w bit is ?0?, the ak4626a generates the acknowledge and the write operation is executed. if r/w bit is ?1?, the ak4626a generates the not acknowledge since the ak4626a can be only a slave-receiver. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 22). the second byte consists of the address for control registers of the ak4626a. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 20). those data after the second byte contain control data. the format is msb first, 8bits (figure 20). the ak4626a generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 20). the ak4626a is capable of more than one byte write operation by one sequence. after receipt of the third byte, the ak4626a generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 23) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w a c k figure 17. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 18. the first byte * * * a4 a3 a2 a1 a0 (*: don?t care) figure 19. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 20. byte structure after the second byte
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 30 - scl sda stop condition start condition s p figure 21. start and stop conditions scl from master acknowledge data output by master data output by slave(ak4529) 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 22. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 23. bit transfer on the i 2 c-bus
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 31 - ? mapping of program registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smute 01h control 2 0 dfs1 loop1 loop0 sdos dfs0 acks 0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 08h de-emphasis 0 0 dema1 dema0 demb1 demb0 demc1 demc0 09h att speed & reset control 0 0 ats1 ats0 0 0 0 rstn 0ah zero detect ovfe dzfm3 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan note: for addresses from 0bh to 1fh, data is not written. when pdn goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the internal timing is reset and dzf1-2 pins go to ?h?, but registers are not initialized to their default values. smute, dfs0, sdos and tdm0 are ored with pins.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 32 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smute default 0 0 0 0 1 0 0 0 smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted register bit of smute is ored with the smute pin if p/s = ?l?. dif1-0: audio data interface modes (see table 8, 9, 10) initial: ?10?, mode 2 tdm1-0: tdm format select (see table 8, 9, 10) mode tdm1 tdm0 sdti sampling speed 0 0 0 1-3 normal, double, four times speed 1 0 1 1 normal speed 2 1 1 1-2 normal, double speed register bit of tdm0 is ored with the tdm0 pin if p/s = ?l?. tdm0 pin should be ?l? if the register control is used.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 dfs1 loop1 loop0 sdos dfs0 acks 0 default 0 0 0 0 0 0 0 0 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs are ignored. when this bit is ?0?, dfs0, 1 set the sampling speed mode. dfs1-0: sampling speed mode (see table 1.) register bit of dfs0 is ored with dfs0 pin if p/s = ?l?. the setting of dfs is ignored at acks bit ?1?. sdos: sdto source select 0: adc 1: daux register bit of sdos is ored with sdos pin if p/s = ?l?. sdos should be set to ?0? at tdm bit ?1?. in the case of pwadn=?0? and pwdan=?0?, the setting of sdos becomes invalid. and adc is selected. the output of sdto becomes ?l? at pwadn=?0?. loop1-0: loopback mode enable 00: normal (no loop back) 01: lin lout1, lout2, lout3 rin rout1, rout2, rout3 the digital adc output (daux input if sdos = ?1?) is connected to the digital dac input. in this mode, the input dac data to sdti1-3 is ignored. the audio format of sdto at loopback mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively. 10: sdti1(l) sdti2(l), sdti3(l) sdti1(r) sdti2(r), sdti3(r) in this mode the input dac data to sdti2-3 is ignored. 11: n/a loop1-0 should be set to ?00? at tdm bit ?1?. in the case of pwadn=?0? and pwdan=?0 ?, the setting of loop1-0 becomes invalid. and adc is selected. and it becomes the n ormal operation (no loop back).
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h lout1 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 a tt6 att5 att4 att3 att2 att1 att0 default 0 0 0 0 0 0 0 0 att7-0: attenuation level (see table 13.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h de-emphasis 0 0 dema1 dema0 demb1 demb0 demc1 demc0 default 0 0 0 1 0 1 0 1 dema1-0: de-emphasis response control for dac1 data on sdti1 (see table 7.) initial: ?01?, off demb1-0: de-emphasis response control for dac2 data on sdti2 (see table 7.) initial: ?01?, off demc1-0: de-emphasis response control for dac3 data on sdti3 (see table 7.) initial: ?01?, off
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h att speed & reset control 0 0 ats1 ats0 0 0 0 rstn default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. dzf1-2 pins go to ?h?, but registers are not initialized. 1: normal operation ats1-0: digital attenuator transition time setting (see table 14.) initial: ?00?, mode 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah zero detect ovfe dzfm3 dzfm2 dzfm1 d zfm0 pwvrn pwadn pwdan default 0 0 1 1 1 1 1 1 pwdan: power-down control of dac1-3 0: power-down 1: normal operation pwadn: power-down control of adc 0: power-down 1: normal operation pwvrn: power-down control of reference voltage 0: power-down 1: normal operation dzfm3-0: zero detect mode select (see table 11.) initial: ?0111?, disable ovfe: overflow detection enable 0: disable, pin#33 becomes dzf2 pin. 1: enable, pin#33 becomes ovf pin.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 36 - system design figure 24 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: tvdd=5v, 3-wire serial control mode, cad1-0 = ?00? tdm0 44 43 42 41 40 39 38 37 36 35 34 sdos 1 2 3 4 5 6 7 8 9 11 10 i2c bick lrck sdti1 sdti2 sdti3 sdto daux dfs0 rin cdti ccl k mcl k dzf1 avss vrefh avdd vcom tst1 dzf2 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 dvdd dzfe tvdd dvss tst2 cad1 cad0 tst3 tst4 lin nc tst5 rout1 lout1 rout2 lout2 rout3 lout3 ak4626a + 0.1u 0.1u 2.2u + 5 up a nalog ground digital ground (dir) dsp a nalog 5v + 10u a udio (mpeg/ a c3) digital a udio source pdn csn p/s smute 0.1u 10u mute mute mute mute mute mute power-down control figure 24. typical connection diagram
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 37 - analog ground digital ground system controller tdm0 sdos 1 2 3 4 5 6 7 8 9 11 10 i2c bick lrck sdti1 sdti2 sdti3 sdto daux dfs0 rin loop0/sda/cdti dif1/scl/ccl k mcl k dzf1 avss vrefh avdd vcom tst1 dzf2/ovf 12 13 14 15 16 17 18 19 20 21 22 dvdd dzfe tvdd dvss tst2 cad1 cad0 tst3 tst4 lin nc tst5 rout1 lout1 rout2 lout2 rout3 lout3 ak4626a pdn dif0/csn p/s smute 33 32 31 30 29 28 27 26 25 23 24 44 43 42 41 40 39 38 37 36 35 34 figure 25. ground layout note: avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling the ak4626a requires careful attention to power suppl y and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the ak4626a must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4626a as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of vrefh sets the analog input/output range. vrefh pin is normally connected to avdd with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vrefh and vcom pins in order to avoid unwanted coupling into the ak4626a. 3. analog inputs adc inputs are single-ended and internally biased to vcom. the input signal range scales with the supply voltage and nominally 0.62 x vrefh vpp (typ)@fs=48khz. the adc output data format 2?s compliment. the dc offset is removed by the internal hpf. the ak4626a samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the ak4626a includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs.
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 38 - 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv. ? peripheral i/f example the ak4626a can accept the signal of device with a nominal 3.3v supply because of ttl input. the power supply for output buffer (tvdd) of the ak4626a should be 3.3v when the peripheral devices operate at a nominal 3.3v supply. figure 26 shows an example with the mixed system of 3.3v and 5v. 3.3v analog 5v analog 3.3v digital 5v digital pll i/f a udio signal dsp a k4112b a nalog digital control signal up & others a k4626a 5v for input 3.3v for output figure 26. power supply connection example
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 39 - package 0.15 0.17 0.10 10.00 1.70max 111 23 33 44 p in lqfp ( unit: mm ) 10.00 12.80 0.30 34 44 0.80 22 12 12.80 0.30 0 0.2 0 10 0.60 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak4626a] ms0397-e-00 2005/06 - 40 - marking a k4626 a vq xxxxxxx 1 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4626AVQ 4) asahi kasei logo revision history date (yy/mm/dd) revision reason page contents 05/06/03 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4626AVQ

	To Download AK4626AVQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .